1. Technical Field
Embodiments relate to a semiconductor integrated circuit device having a vertical channel and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit device having a vertical channel of a wrap-around contact structure and a method of manufacturing the same.
2. Related Art
Memory devices are generally provided as internal semiconductor integrated circuit devices of computers or other electronic apparatuses. As is well-known, typical examples of memory devices include random access memories (RAMs), read only memories (ROMs), dynamic RAMs (DRAMs), synchronous DRAM (SDRAM), flash memories, and variable resistive memory devices. Variable resistive memory devices may include programmable conductive memory devices, resistive RAMs (ReRAMs), and phase-change RAMs (PCRAMs).
Nonvolatile memory devices such as PCRAMs may be used in broad electronic applications to provide high integration density, high reliability, and low power consumption.
A variable resistive memory device is one example of the nonvolatile memory device. The variable resistive memory device may include a plurality of memory cells arranged in a matrix form. The memory cell may include an access device such as a diode, a field effect transistor (FET), or a bipolar junction transistor (BJT), and may be coupled to a word line which is arranged along a row of an array. Memory elements in the memory cells may be coupled to a bit line which is arranged along a column of the array. The access device of the memory cell may select a word line coupled to a gate in a given memory cell and the given memory cell may be accessed through a row decoder which activates the row to which the given memory cell is coupled.
Currently, a transistor having a 3D vertical channel structure is preferred as the access device of the memory cell due to its ability to promote high integration density. As is well-known, the transistor having the 3D vertical channel structure may include a pillar-shaped active region, a gate formed on a circumference of the active region, a drain formed in an upper portion of the active region and located at a higher level than the gate, and a source formed in a lower portion of the active region and located at a lower level than the gate. Alternatively, the source may be formed in a semiconductor substrate which is in contact with the lower portion of the active region. A heating electrode, a variable resistance layer, and a bit line are sequentially formed and they are electrically coupled to the drain of the transistor, and thus the resistive memory cell is completed.
To obtain an ohmic contact between the drain and the heating electrode, a silicide layer for an ohmic contact layer is formed between the drain and the heating electrode. Currently, endeavors for improving operation current in the variable resistive memory device continue, and thus technology for improving the contact area between the drain and the silicide layer has been suggested.